Western Digital has announced its successful development of four bits per cell, X4, flash memory architecture offering on 64-layer 3D NAND, BiCS3, technology. Building on its pioneering innovation of X4 for 2D NAND technology and past success in commercializing it, the company has now developed X4 for 3D NAND by leveraging its deep vertical integration capabilities.
These include silicon wafer processing, device engineering to provide sixteen distinct data levels in every storage node, and system expertise for overall flash management. BiCS3 X4 technology delivers an industry-leading storage capacity of 768 gigabits on a single chip, a 50 percent increase from the prior 512 gigabit chip that was enabled with the three bits per cell (X3) architecture.
“The implementation of X4 architecture on BiCS3 is a significant development for Western Digital as it demonstrates our continued leadership in NAND flash technology, and it also enables us to offer an expanded choice of storage solutions for our customers,” said Dr. Siva Sivaram, executive vice president, Memory Technology, Western Digital.
“The most striking aspect in today’s announcement is the use of innovative techniques in the X4 architecture that allows our BiCS3 X4 to deliver performance attributes comparable to those in BiCS3 X3. The narrowing of the performance gap between the X4 and X3 architectures is an important and differentiating capability for us, and it should help drive broader market acceptance of X4 technology over the next several years.”
This latest achievement follows a nearly three-decade long legacy of industry firsts in flash innovation, including the industry’s multi-level cell (MLC) flash technologies using two bits (X2) and three bits (X3) per cell.
The company expects to productize its 3D NAND X4 technology across multiple end-use applications that can take advantage of the higher capacity points supported by X4. Future generations of 3D NAND technology, including the 96-layer BiCS4, are also expected to feature X4 capabilities.